1. Field of the Invention
The present invention relates to a circuit specification description visualizing device, a circuit specification description visualizing method and a storage medium. In particular, it relates to a circuit specification description visualizing device, a circuit specification description visualizing method and a storage medium configured to design a semiconductor integrated circuit using a circuit specification description.
2. Description of Related Art
According to prior art, a semiconductor integrated circuit is designed based on a circuit specification described using a natural language or a property description language.
However, when the circuit specification is described using a natural language, polysemy or ambiguity of the natural language can cause disagreement in interpretation among the designers, which can lead to an inoperative circuit or other problems. Using a property description language (such as SVA and PSL) to describe the circuit specification can help solve the problem of the polysemy or ambiguity of the description. However, it is only a partial and inadequate solution.
For example, a circuit specification that “if req is asserted, ack is asserted” written in a natural language cannot be converted into a property description language if the polarity of the signals and the number of req/ack cycles are ambiguous. Therefore, typically, the ambiguity is eliminated before the natural language is converted into the property description language.
However, even if the circuit specification is described in the property description language, the polysemy or ambiguity of the circuit specification description cannot necessarily be eliminated enough. For example, when a circuit specification that “if req is asserted, ack is asserted” described in the natural language is converted into a circuit specification that “req|=>ack” described in SVA, which is a property description language, it remains obscure whether req is 1 or 0 in a cycle following a cycle in which req is 0 or whether ack is 1 or 0 in a cycle preceding a cycle in which ack is 1. In the natural language, the circuit specification “req|=>ack” means that when req is 1 in a cycle, ack is 1 in the immediately following cycle. Furthermore, the status of req in a cycle preceding a cycle in which req is 1, that is, whether req is 1 or 0 in a cycle preceding a cycle in which req is 1, also remains obscure.
In other words, even the circuit specification described in the property language described above can have a plurality of signal patterns, or in other words, pass patterns for one circuit specification description. However, the designer does not have means to recognize the level of ambiguity of the circuit specification description written by the designer themselves. As a result, in many cases, the intention of the designer is not correctly interpreted, and the failures described above occur.
For example, as disclosed in Japanese Patent Application Laid-Open Publication No. 5-101132, a logic circuit operation testing device is proposed, which is configured to smoothly and efficiently test a circuit to be designed. However, the patent literature does not disclose any method of allowing a designer to recognize the level of ambiguity of a circuit specification description written by the designer themselves.
In addition, it is also hard to recognize a correlation between each partial expression in the circuit specification and a part of a signal waveform. Therefore, the designer cannot easily understand the meaning of an assertion and modify the assertion.